Phase locked loop
US6353647B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 1998 |
| Grant date | Mar 5, 2002 |
| Priority date | — |
| Expiry date | Apr 17, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/1075
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase-locked loop having very fast acquisition, and low output phase jitter and stability at steady-state is provided. In general, the phase-locked loop is used for synchronizing an output signal of said phase-locked loop with an input reference signal. The filter circuit of the phase-locked loop includes a differentiator responsive to the phase difference representing signal from a phase detector in the PLL for providing a differentiated signal, and a filter responsive to both the phase difference representing signal and the differentiated signal to provide a filter output signal. Preferably, the filter is a low-pass filter. The output signal source of the PLL is controlled by a control signal which is generally based on the filter output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.