Directory cache for indirectly addressed main memory
US6353871B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 1999 |
| Grant date | Mar 5, 2002 |
| Priority date | — |
| Expiry date | Feb 22, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/654
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system including a CPU, memory, and compression controller hardware, and implementing a first directory structure included in a first memory wherein CPU generated real memory addresses are translated into one or more physical memory locations using the first directory structure, further includes a second directory cache structure having entries corresponding to directory entries included in the first directory structure. In a first embodiment, the second directory cache structure is implemented as part of compression controller hardware. In a second embodiment, a common directory and cache memory structure is provided for storing a subset of directory entries in the directory structure together with a subset of the memory contents.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.