Semiconductor integrated circuit and recording medium
US6353905B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 30, 2000 |
| Grant date | Mar 5, 2002 |
| Priority date | — |
| Expiry date | Jun 30, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318544
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Disclosed herein are a semiconductor integrated circuit and a recording medium wherein the amount of test data inputted from and outputted to the outside to test a plurality of circuit modules and the amount of test result data are reduced and a test time interval is shortened. When each of tested circuits is tested, test control information is externally inputted to a test interface circuit, and test control information is set to each of scan registers of circuit modules to be tested, through a test signal chain. When an instruction for a test operation is given to each of test control circuits through a control terminal, a test circuit allows the tested circuits to be tested based on the test control information on a parallel basis. Test results are read into the test interface circuit from the scan registers through the test signal chain, followed by output to the outside. The test operations for the circuit modules can be parallelized and the test interface circuit can be shared between the respective circuit modules.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.