Testing synchronization circuitry using digital simulation
US6353906B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 1998 |
| Grant date | Mar 5, 2002 |
| Priority date | — |
| Expiry date | Apr 1, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31922
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
To vigorously test synchronization logic and protocols in a digital circuit design, a synchronization logic model uses randomization to emulate the uncertainty in synchronization clock delay time exhibited in actual circuits. The synchronization logic model is inserted into a software description of the design so that simulation will reveal faulty assumptions in the synchronization protocol. Additionally, where a non-synchronized signal crosses from one clock domain to another clock domain in an asynchronous digital design, a transition on the non-synchronized signal triggers an “X” value window on the signal for a selected period relative to the receiving clock period, so that simulation will fail if the receiving logic samples the signal value during the “X” value window. These techniques aid in effective testing of the design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.