Determining a worst case switching factor for integrated circuit design
US6353917B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 1, 1999 |
| Grant date | Mar 5, 2002 |
| Priority date | — |
| Expiry date | Sep 1, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Determining a switching factor is useful for optimizing integrated circuit (IC) design. One aspect of the invention is a method for determining the switching factor. The method includes applying a voltage to each interconnect of a pair of interconnects, each voltage having a waveform and a slew time. The method includes dividing the voltage waveform into time regions, and analyzing a behavior of a capacitor in each of the time regions by determining the value of an effective capacitance as seen from one of the interconnects. The method includes determining a total effective capacitance by time averaging the effective capacitance values and determining the switching factor from the total effective capacitance. The switching factor is a function of a ratio between the slew times, wherein a time-averaged effective value of the switching factor corresponds total effective capacitance. The time-averaged effective value of the switching factor is accounted for in optimizing the design of IC comments interconnections. The switching factor has a value that varies between zero (0) and a switching factor maximum value based on logic state switching conditions of the voltages including their …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.