Method to increase coupling ratio of source to floating gate in split-gate flash
US6355527B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 19, 1999 |
| Grant date | Mar 12, 2002 |
| Priority date | — |
| Expiry date | May 19, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
A method is provided for forming a split-gate flash memory cell having reduced size, increased coupling ratio and improved program speed. A split-gate cell is also provided where the a first polysilicon layer forms the floating gate disposed over an intervening intergate oxide formed over a second polysilicon layer forming the control gate. However, the second polysilicon layer is also formed over the source region and overlying the other otherwise exposed portion of the floating gate such that this additional poly line now shares the voltage between the source and the floating gate, thereby reducing punch-through and junction breakdown voltages. In addition, the presence of another poly wall along the floating gate increases the coupling ratio between the source and the floating gate, which in turn improves program speed of the split-gate flash memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.