Crosspoint switch array with broadcast and implied disconnect operating modes
US6356111B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 12, 2000 |
| Grant date | Mar 12, 2002 |
| Priority date | — |
| Expiry date | Dec 12, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q2213/13305
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A high-speed N×M crosspoint switch selectively routes input signals arriving at any of N input terminals to one or more of M output terminals through a switch cell array having N rows and M columns of switch cells, each for selectively providing a signal path between one input terminal and one output terminal. Each switch cell contains a first memory cell holding a data bit, a second memory cell holding a control bit, and a transistor for making or braking a signal path in response to the control bit. This switch cell architecture enables the crosspoint switch to operate in normal, implied disconnect and broadcast modes. In the normal mode a controller creates a routing pattern by writing data bits to the second memory cells and then signals all switch cells to transfer their data bits into the first memory cells. In the implied disconnect mode, when any cell of a column is signaled to make a path, all other cells along that column automatically break their paths. The broadcast mode allows the controller to quickly configure the array to broadcast a signal and then restore a previous routing pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.