Method and circuitry for supplying clock to internal circuit
US6356128B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 25, 2001 |
| Grant date | Mar 12, 2002 |
| Priority date | — |
| Expiry date | Jan 25, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0891
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Clock supply circuitry comprises a phase-locked loop or PLL frequency multiplier for generating a frequency-multiplied clock signal having a frequency that is an integral multiple of the frequency of an input clock signal. The clock supply circuitry further includes a PLL output stability detecting circuit. When the clocksupply circuitry is made to return from a clock supply stopping state in which the PLL frequency multiplier is stopping the generation of the frequency-multiplied clock signal to a clock supply state in which the PLL frequency multiplier is generating and supplying the frequency-multiplied clock signal to an internal circuit, the PLL output stability detecting circuit determines whether the frequency-multiplied clock signal from the PLL frequency multiplier becomes stable. After the PLL output stability detecting circuit determines that the frequency-multiplied clock signal becomes stable, it supplies the frequency-multiplied clock signal from the PLL frequency multiplier as a system clock signal to the internal circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.