Single clock reference for compressed domain processing systems
US6356212B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 18, 2000 |
| Grant date | Mar 12, 2002 |
| Priority date | — |
| Expiry date | Feb 18, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N21/4305
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A device and method for utilizing a single clock signal to generate a digital data stream signal for transmission in a compressed domain transmission system. The device includes a plurality of packetized elementary stream encoders electronically coupled to a transport stream encoder electronically coupled to an output interface adapted to generate the digital data stream signal. The method includes: operating each of the packetized elementary stream encoders responsively to the single clock sequence to generate a plurality of packetized elementary stream signals; operating the transport stream encoder responsively to the single clock signal to form a transport stream signal from the plurality of packetized elementary stream signals, wherein the transport stream signal includes a plurality of data packets each formed using the transport stream encoder and select ones of the plurality of data packets formed by the transport stream encoder include synchronization data; and, operating the output interface responsively to the single clock reference to output the digital data stream signal in compliance with an predefined manner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.