Flash based control for field programmable gate array
US6356478B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 21, 2000 |
| Grant date | Mar 12, 2002 |
| Priority date | — |
| Expiry date | Dec 21, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0441
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit for controlling a switching transistor in a reprogrammable FPGA device comprises first and second floating gate flash memory transistors. A first floating gate flash memory transistor has a drain electrically coupled to a first voltage potential, a floating gate, a control gate coupled to a control gate node, and a source coupled to an output node. A second floating gate flash memory transistor has a drain electrically coupled to the output node, a floating gate, a control gate coupled to the control gate node, and a source coupled to a second voltage potential. The output node is coupled to the gate of a switching transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.