Merging write cycles by comparing at least a portion of the respective write cycle addresses
US6356485B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 12, 2000 |
| Grant date | Mar 12, 2002 |
| Priority date | — |
| Expiry date | Feb 12, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/488
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A high performance dynamic memory array architecture is disclosed in several embodiments, along with various embodiments of associated supporting circuitry. An exemplary 18 MBit memory array integrated circuit includes four banks of arrays and a write queue for storing at least one pending write cycle. At least a portion of the address information associated with a pending internal write operation is compared to corresponding address information associated with a subsequently-received write cycle request to determine whether a first group of memory cells to be otherwise written by the pending internal write operation and a second group of memory cells to be otherwise written by another internal write operation corresponding to a subsequently-received write cycle request may instead be both written using a single internal write operation. If so, then the pending internal write operation is skipped, the write data associated with the subsequently-received write cycle request is merged into, and supersedes any commonly-addressed data bits of, the write data associated with the pending internal write operation, and a single internal write operation is performed to write the merged data…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.