Synchronous DRAM using column operation sychronous pulses which are different between read and write
US6356507B1 · kind B1 · utility
7Cited by
2References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 21, 2000 |
| Grant date | Mar 12, 2002 |
| Priority date | — |
| Expiry date | Sep 21, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q9/14
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
To provide a semiconductor memory for synchronizing input of a command except for POWER-DOWN-EXIT or the like and write or read of data with an external clock and generating a column operation synchronous pulse having the same number as that of a burst length within the semiconductor memory by using an internal operation synchronous pulse having this external clock as a trigger and after activation of a column system circuit, using the internal operation synchronous pulse as a trigger. This semiconductor memory uses column pulse transfer signals, which are different between read and write to control a column system circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.