Clock signal reproducing apparatus
US6356612B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 1, 1998 |
| Grant date | Mar 12, 2002 |
| Priority date | — |
| Expiry date | Dec 1, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0334
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Analog-to-digital converter 8 samples demodulated data signal 110 inputted from input terminal 14 in synchronism with clock signal 12 and converts the demodulated data signal into digital signal 9. Signal variation direction detection circuit 6 detects whether demodulated data signal 110 ascends or descends in one cycle of clock signal 12. Oscillator control circuit 10 supplies oscillator 4 with control voltage 5 corresponding to the amplitude of digital signal 9, and oscillator control circuit 10 switches whether to ascend or descend control voltage 5 as digital signal 9 increases on the basis of a variation direction signal 7. As a result, clock signal 12 generated by oscillator 4 has a frequency equal to the bit rate of demodulated data signal 110 and a phase fixed to demodulated data signal 110, and it is outputted from output terminal 122 as a clock signal reproduced from demodulated data signal 110.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.