Method and apparatus for determining continuity and integrity of a RAMBUS channel in a computer system
US6357018B1 · kind B1 · utility
54Cited by
18References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 26, 1999 |
| Grant date | Mar 12, 2002 |
| Priority date | — |
| Expiry date | Jan 26, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2284
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system includes at least one processor, at least one memory, and a device for performing a prescribed continuity and integrity check of a memory bus channel having a serial topology. In one embodiment, basic input output system (BIOS) firmware is stored in memory and includes instructions for causing the processor to perform the prescribed continuity and integrity check of the memory bus channel having a serial topology.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.