Integrated circuit interconnect and method
US6358849B1 · kind B1 · utility
38Cited by
3References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 21, 1999 |
| Grant date | Mar 19, 2002 |
| Priority date | — |
| Expiry date | Dec 21, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76867
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A dual inlaid interconnect fabrication method using a temporary filler in a via during trench etch and removal of the filler after trench etch. This provides via bottom protection during trench etch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.