Resin sealed semiconductor device, circuit member for use therein
US6359221B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 1998 |
| Grant date | Mar 19, 2002 |
| Priority date | — |
| Expiry date | Aug 1, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49172
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
There is disclosed a resin-sealed semiconductor device in which plural circuit portions integrally having inner and outer terminals are arranged two-dimensionally substantially in a plane and electrically independent of one another, and have leads for integrally interconnecting the inner and outer terminals, surfaces of the circuit portions are semiconductor element mounted faces with the inner and outer terminals and the leads forming one plane, the inner terminals and the leads are thinner than the outer terminals, back surfaces of the circuit portions are provided with terminal faces of the inner and outer terminals, a terminal mounted face of the semiconductor element is mounted via an insulating layer onto the semiconductor element mounted faces of the circuit portions, and the semiconductor element terminals are electrically connected with wires to the terminal faces of the inner terminal, and the whole is sealed with a resin in such a manner that the outer terminals are partially exposed to the outside. An occupation ratio of the semiconductor element in the semiconductor device is enhanced, the semiconductor device can be miniaturized, and a mounting density onto a circuit …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.