Method and apparatus to prevent latch-up in CMOS devices

US6359316B1 · kind B1 · utility

Assignee

• Cypress Semiconductor Corporation · US

Inventors

• Peter Voss · Aromas, US
• Andrew J. Walker · Mountain View, US
• Jeff Watt · Mountain View, US
• Ashish Pancholy · Milpitas, US
• Cathal G. Phelan · Mountain View, US
• Patrick Zicolello · Santa Clara, US
• Christopher J. Petti · Mountain View, US

Key dates

• Filing date: Sep 19, 1997
• Grant date: Mar 19, 2002
• Expiry date: Sep 19, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

A semiconductor (preferably a CMOS) device having one or more latch-up inhibitor diffusion regions. The latch-up inhibitor regions are adjacent to complementary P-channel and N-channel transistors, and typically function to inhibit or prevent latch-up, without increasing the die size of the device.