Reduced-undershoot CMOS output buffer with delayed VOL-driver transistor
US6359478B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 31, 2001 |
| Grant date | Mar 19, 2002 |
| Priority date | — |
| Expiry date | Aug 31, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00361
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A large pull-down voltage-output-low VOL transistor is placed in parallel with a smaller pull-down switching transistor. The smaller switching pull-down transistor is turned on during switching. Once switching has nearly completed, the larger pull-down VOL transistor is turned on to provide a current sink for maintaining a VOL close to ground. Switching current is limited by the smaller switching pull-down transistor, while a large static sink current is provided by the VOL transistor to meet VOL requirements. The gate of the VOL transistor is controlled by p-channel and n-channel data transistors that are controlled by the data input, and p-channel and n-channel feedback transistors with gates connected to the buffer output. An upper n-channel transistor provides current to an intermediate node at the drain of the p-channel feedback transistor, keeping it near an intermediate voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.