Automatic lockup low-voltage biasing circuit
US6359497B1 · kind B1 · utility
12Cited by
3References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 20, 2000 |
| Grant date | Mar 19, 2002 |
| Priority date | — |
| Expiry date | Apr 20, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/2481
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Presented is a low-voltage automatic lock-up biasing circuit with input terminals that accept input voltages, and with an internal node coupled to both input terminals an which takes take the highest of the voltage values applied to the input terminals. This circuit uses a comparator having respective inputs connected to the input terminals and with an output connected to a level shifter. Outputs of the level shifter are coupled to respective enable elements connected between each input terminal and the internal node. The enable elements are driven each by a respective output of the level shifter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.