CMOS power amplifier with reduced harmonics and improved efficiency
US6359513B1 · kind B1 · utility
80Cited by
5References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2001 |
| Grant date | Mar 19, 2002 |
| Priority date | — |
| Expiry date | Jan 31, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/604
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A CMOS Class F amplifier uses a differential input to eliminate even-order harmonics, thereby avoiding the need for circuits that are tuned to the second harmonic. This also minimizes the sensitivity of the design to changes in the second harmonic frequency and/or the particular component values selected for the tuned circuit. Third-order harmonics are reduced by controlling the phase relationship between the differential inputs. Additional efficiency is achieved by dynamically controlling the impedance of the amplifier as a function of output power level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.