One-transistor and one-capacitor DRAM cell for logic process technology
US6359802B1 · kind B1 · utility
119Cited by
4References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2000 |
| Grant date | Mar 19, 2002 |
| Priority date | — |
| Expiry date | Mar 28, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell including two switching devices, a bit line and a word line. The first switching device has an enable input. The second switching device is configured to store a charge, which deactivates the second switching device. The bit line is coupled to the first switching device. The first switching device is coupled to second switching device. The word line is coupled to the enable input of the first switching device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.