Storage cell on integrated circuit responsive to plural frequency clocks
US6359830B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Feb 18, 2000 |
| Grant date | Mar 19, 2002 |
| Priority date | — |
| Expiry date | Feb 18, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/229
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit chip responds to clock waves having differing frequencies at different times. The chip includes a semiconductor memory cell having a write enable input terminal responsive to a write enable signal having first and second levels. The cell has a tendency to operate improperly in response to the first level of the write enable signal having an excessively long predetermined duration. A write enable signal source responds to the clock waves so that for clock waves having half cycles of duration less than the predetermined duration the first level of the write enable signal has durations approximately equal to the durations of the half cycles of these clock waves. For clock waves having half cycles of duration greater than the predetermined duration, the first level of the write enable signal has a duration substantially equal to the predetermined duration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.