Asynchronous data receiving circuit and method
US6359943B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 13, 1999 |
| Grant date | Mar 19, 2002 |
| Priority date | — |
| Expiry date | Dec 13, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/08
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In accordance with this invention, a data capture circuit of a data receiver captures data from a data stream of a data transmitter operating at a different phase or frequency from the system clock of the data receiver. In one embodiment, the data receiver determines the number of clock periods of a clock signal in a data period of the data stream. Specifically, a signal detection circuit receives a signal having a periodic and distinctive feature. The period of the periodic and distinctive feature is related to the data period by a fixed scaling factor. A counter counts the number of clock periods of the clock signal between a first occurrence of the periodic and distinctive feature and a second occurrence of the periodic and distinctive feature. A multiplier/divider circuit divides or multiples the content of the first counter by the scaling factor to determine the integer clock period count. The results of the multiply or divide is stored in a count register. In some embodiments of the data receiver an integer error compensation circuit compensates for the difference between the actual number of clock periods in a data period and the integer clock period count. A divider divides…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.