Apparatus for determining memory bank availability in a computer system
US6360285B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 1994 |
| Grant date | Mar 19, 2002 |
| Priority date | — |
| Expiry date | Jun 30, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In accordance with the present invention, an apparatus includes a system bus having memory bank available signals. Coupled to the system bus are at least two memory modules, each having at least one memory bank. Each memory module includes a mechanism for associating each memory bank with one of the memory bank available signals. Further, each memory module includes logic for determining an availability status of each memory bank and for providing the associated memory bank busy signal with values reflecting the availability status of the memory bank. Additionally, at least two commander modules are coupled to the system bus and include logic, responsive to the memory bank available signals for preventing the commander module from gaining control of the system bus when the commander is attempting to access a memory bank determined to be unavailable. With such an arrangement, only commander modules seeking to access memory banks which are available will be allowed to gain control of the system bus. This avoids stalling the system bus and improves system performance by allowing all initiated transactions to complete as quickly as possible.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.