Method and apparatus for determining a processor failure in a multiprocessor computer
US6360333B1 · kind B1 · utility
33Cited by
18References
67Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 19, 1998 |
| Grant date | Mar 19, 2002 |
| Priority date | — |
| Expiry date | Nov 19, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2046
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiprocessor computer includes a fault detection scheme which detects and identifies the failure of one of the processors. Each processor is assigned a write location, which may be a unique register. During normal computer operation, each processor intermittently performs a test and stores the results of the test in the assigned write location. The stored results are compared to expected results, and an error signal is generated if the stored results differ from the expected results to indicate that one of the processors has failed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.