Memory tester with data compression
US6360340B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 1996 |
| Grant date | Mar 19, 2002 |
| Priority date | — |
| Expiry date | Nov 19, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/44
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A semiconductor memory test system with improved fault data processing and display capabilities. The memory tester includes a lossless data compressor for failure data. Compression allows failure data to be more rapidly transferred to a display device that is part of a work station controlling the memory tester. It also reduces the amount of data that must be stored in the display memory, thereby providing a cost effective way to store data from multiple tests. By allowing data for multiple tests to be stored, the data from a prior test can be used to control the formatting of data for a subsequent test. Such formatting is useful for such things as observing failure mechanisms as the operating temperature or speed of the semiconductor memory under test increases.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.