Digital circuit layout techniques
US6360352B2 · kind B2 · utility
21Cited by
7References
20Claims
0Family size
Inventor
Key dates
| Filing date | Jul 17, 1998 |
| Grant date | Mar 19, 2002 |
| Priority date | — |
| Expiry date | Jul 17, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique for analyzing digital circuits to identify pin swaps is provided for circuit layout and similar tasks in which the circuit is first decomposed into fanout-free regions. Quasi-canonical forms or models of the fanout free region are created from which a swap structure is created so that pins swap groups can be identified.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.