Single step etched moat
US6362112B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 8, 2000 |
| Grant date | Mar 26, 2002 |
| Priority date | — |
| Expiry date | Nov 8, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3083
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A single step etched moat (24), having a regular grid work mask (28) of mesa shields (42) and edge termination shields (44), is utilized to form, in a single etching step, semiconductor devices (22) having lengthy edge terminations for reduced edge termination failure. The desired semiconductor devices (22) include a high resistivity, monocrystalline grown substrate layer (30), a low resistivity epitaxial base layer (32), and a low resistivity top layer (36). The regular grid work of mesa shields (42) and edge termination shields (44) define open grid lines (48) and open grid rings (46). The open grid lines (48) are wider than the open grid rings (46), so that as the moats (24) are etched, a deeper grid line divot (50) is formed below the open grid lines (48) and a more shallow grid ring divot is formed below the open grid ring (46).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.