High voltage package for electronic device
US6362517B1 · kind B1 · utility
Inventors
Key dates
| Filing date | Sep 22, 1999 |
| Grant date | Mar 26, 2002 |
| Priority date | — |
| Expiry date | Sep 22, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An improved package for a semiconductor device. The semiconductor device includes an apparatus having at least two access leads to facilitate electrical connection of the apparatus within an electrical circuit. The package has generally a closed polyhedral shape presenting a plurality of faces and substantially insulatingly surrounding the apparatus in a manner leaving the access leads exposed for effecting electrical connection. The access leads extend a distance from exit loci from the package. The exit loci are situated on an exit face of the package, adjacent pairs of exit loci being generally in a common plane. An intraplanar distance within the common plane is established intermediate each adjacent pair of the exit loci. The improvement comprises configuring the exit face to establish an on-surface path greater than the intraplanar distance intermediate selected adjacent pairs of the exit loci.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.