Field programmable gate array with mask programmed input and output buffers
US6362649B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 2, 1999 |
| Grant date | Mar 26, 2002 |
| Priority date | — |
| Expiry date | Apr 2, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17788
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A hybrid integrated circuit architecture comprising a mask programmable portion and a field programmable gate array portion. The mask programmable portion has a plurality of mask programmed input and output buffer circuits, and a first group of input/output pads, wherein one of the input/output pads of the first group is connected to an input of one of the input buffer circuits, and one of the input/output pads of the first group is connected to an output of one of the output buffer circuits. The field programmable gate array portion has programmable digital logic function modules, a second group of input/output pads, interconnect conductors divided into one or more segments, wherein some segments run in a first direction and some segments run in a second direction to form intersections and some segments form intersections with inputs and outputs of the digital logic function modules, the first group of input/output pads, and inputs and outputs of the output and input buffer circuits from the mask programmable portion, and user programmable interconnect elements connected between adjoining ones of the segments in a same one of the interconnect conductors, and between intersections …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.