High voltage buffer for submicron CMOS
US6362652B1 · kind B1 · utility
13Cited by
52References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 20, 1999 |
| Grant date | Mar 26, 2002 |
| Priority date | — |
| Expiry date | Dec 20, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00315
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An input circuit allows input buffers fabricated using submicron CMOS technologies to receive input signals having a voltage swing of 5V. The input circuit uses a cascode transistor to bias the drain of the input transistor so that the VGD of the input transistor does not reach or exceed the gate-oxide breakdown voltage. Outputs of the input buffers have a maximum voltage that is limited by their respective supply voltages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.