Digital communications modulator having an interpolator upstream of a linearizer and method therefor
US6362701B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 9, 2000 |
| Grant date | Mar 26, 2002 |
| Priority date | — |
| Expiry date | Nov 9, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/2071
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An IC modulation processor (28) may be configured to operate in a single chip mode to accommodate baud rates up to a maximum clock rate for the processor (28) and in a dual chip mode to accommodate baud rates in excess of the maximum clock rate. The IC modulation processor (28) performs digital processing on a communication signal which conveys an input data stream (22). A pulse shaping filter (54-57) is provided following a phase mapper (50). The pulse shaping filter (54-57) is implemented as a pair of half-filters. Pulse shaping is distributed between two IC modulation processors (28) in the dual chip mode. An interpolator (86) and linearizer (106) follow the pulse shaping filters (54-57).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.