Dual input switched capacitor gain stage
US6362770B1 · kind B1 · utility
28Cited by
5References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 12, 2000 |
| Grant date | Mar 26, 2002 |
| Priority date | — |
| Expiry date | Sep 12, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/442
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A gain stage using switched capacitor architecture and suitable for a pipelined analog to digital converters provides for three pairs of switched capacitor banks whose use may be alternated so as to provide simultaneous sampling of two input channels for sequential gain operation without the interposition of additional circuitry in the signal chain from input to output of the gain stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.