Multiply-add operating device for floating point number
US6363476B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 11, 1999 |
| Grant date | Mar 26, 2002 |
| Priority date | — |
| Expiry date | Aug 11, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A floating point multiply-add operating device in which a critical path in an addition process of continuous multiply-add operations of floating point numbers is shortened to improve operation efficiency is disclosed. This operating device includes: an exponent operating section for comparing an exponent of a floating point number of an operation result of a preceding multiply-add operation n with an exponent of a multiplication result of a subsequent multiply-add operation (n+1), and calculating an alignment shift count of the multiply-add operation (n+1) by the comparison result; and a mantissa operating section for aligning one mantissa of mantissas of two operands according to the alignment shift count inputted from the exponent operating section, calculating a sum of an aligned mantissa of the operand and the mantissa of the other operand, and normalizing a calculated addition result of the mantissas as needed, thereby calculating a mantissa of the multiply-add operation (n+1). The alignment shift count is obtained by starting calculation of an alignment shift count of the subsequent multiply-add operation (n+1) before normalization of the preceding multiply-add operation n is…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.