Early power estimation tool for high performance electronic system design
US6363515B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 1997 |
| Grant date | Mar 26, 2002 |
| Priority date | — |
| Expiry date | Dec 30, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A power estimation tool allows the designer to estimate power usage, at the RTL stage for example, of a high performance electronic system design using available information. This enables power estimation before the circuit schematics are created and early enough for power dissipation to be included in the design optimization. The estimation tool, operable at the RTL level, may provide estimates of power usage of functional blocks and the overall system. The tool can take an HDL description of the proposed design and partition that description into a format which can be analyzed for power usage in an automated fashion. The estimated power use can also be modified to account for different circuit design techniques such domino versus static designs and to account for capacitance and layout considerations. In addition, an empirical estimator for clock and data buffer power usage allows these elements to be accounted for before their design is completed. The tool uses a power model library of prior designs to efficiently estimate power dissipation of subsequent designs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.