Solid state electronic device fabrication using crystalline defect control
US6365478B1 · kind B1 · utility
2Cited by
3References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 22, 2000 |
| Grant date | Apr 2, 2002 |
| Priority date | — |
| Expiry date | Sep 22, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/12
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
A solid state electronic device (40) comprising a substrate (30) and layers (32 and 34) is fabricated to control the formation of crystalline defects to control at least one characteristic of the device, such as current gain beta. The formation of crystalline defects preferably is controlled by controlling the temperature of the substrate, layers or both.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.