Passivation for tight metal geometry
US6365521B1 · kind B1 · utility
5Cited by
9References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 31, 1997 |
| Grant date | Apr 2, 2002 |
| Priority date | — |
| Expiry date | Dec 31, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of passivating an integrated circuit comprising providing an integrated circuit having a top side including a bond pad, depositing a first dielectric over said top side of said integrated circuit, exposing a first area portion of a top side of said bond pad, depositing a second dielectric of one of a material that is substantially impermeable to moisture over said top side of said integrated circuit, and exposing a second area portion of said top side of said bond pad, said second area portion within said first area portion is disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.