System and method for detecting defects within an electrical circuit by analyzing quiescent current
US6366108B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 1998 |
| Grant date | Apr 2, 2002 |
| Priority date | — |
| Expiry date | Dec 1, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/81
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The present invention, in general, provides for a testing system and method for detecting defects within a circuit. A current signature of the quiescent current of the circuit is determined, and certain constant values are calculated based on the current signature using a linear iterative regression. A defect free state for the circuit associated with a minimum quiescent current (IDDQ) is then determined. The IDDQ of the circuit for this state is measured, and a signal indicating the IDDQ at this state is used along with the aforementioned constant values to create upper and lower threshold values. Thereafter, signals indicating the value of IDDQ for a plurality of other states are compared to the upper and lower threshold values. The circuit is determined to be defective if the values of any of the signals is greater than the upper threshold value or is less than the lower threshold value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.