Configuration for testing chips
US6366110B1 · kind B1 · utility
5Cited by
3References
2Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 14, 1999 |
| Grant date | Apr 2, 2002 |
| Priority date | — |
| Expiry date | Jul 14, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/32
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A configuration is provided for testing chips produced from a wafer. The chips are supplied with test signals through the use of a test head. The test signals can be applied in a serial or parallel manner to the chips which are actually in the wafer, through the use of test lines provided in a sawing edge of the chips.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.