Random access memory
US6366504B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 7, 2000 |
| Grant date | Apr 2, 2002 |
| Priority date | — |
| Expiry date | Jul 7, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A random access memory comprises a matrix made up of cells arranged in rows and columns and the cells are addressed row by row. Each cell of a row is connected to first and second bit lines and at least the first bit line is subdivided into a plurality of sections connected to respective inputs of an output logic gate. The memory includes read/write control circuits which apply the following logic functions to each of the first and second bit lines directly or indirectly and selectively, according to whether a required operation is a write or a read. Sel.((W.D) or {overscore (W)})) is applied to the first bit line, whilst Sel.W.D is applied to both the first and second bits lines, where “Sel” is a cell selection signal representative of the address, “W” is a write command, {overscore (W)} is a read command, “D” is the data to be written into the addressed cell and “.” indicates the AND function.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.