Method and apparatus for rounding floating point results in a digital processing system
US6366942B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 1999 |
| Grant date | Apr 2, 2002 |
| Priority date | — |
| Expiry date | Mar 30, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/485
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for operating on floating point numbers is provided that accepts two floating point numbers as operands in order to perform addition, a rounding adder circuit is provided which can accept the operands and a rounding increment bit at various bit positions. The circuit uses full adders at required bit positions to accommodate a bit from each operand and the rounding bit. Since the proper position in which the rounding bit should be injected into the addition may be unknown at the start, respective low and high increment bit addition circuits are provided to compute a result for both a low and a high increment rounding bit condition. The final result is selected based upon the most significant bit of the low rounding bit increment result. In this manner, the present rounding adder circuit eliminates the need to perform a no increment calculation used to select a result, as in the prior art. Through the use of full adders, the circuit not only accounts for the round increment bit, but can accept increment bits at any bit position to perform operations such as two's complement, thus further reducing the operations required to perform a desired floating point mathe…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.