High availability asynchronous computer system
US6366985B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 22, 2000 |
| Grant date | Apr 2, 2002 |
| Priority date | — |
| Expiry date | Sep 22, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1663
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for receiving status information from shared logical memory modules in a computer system including redundant memory. The status information includes whether the shared logical memory modules are in a transitional state and the number of logical memory modules in the mirror set. When shared logical memory modules are added or removed from redundant memory they go through a transitional state when the memory card may respond to a request for data held on the card, but that data may be unreliable. Checking this status information allows better error checking of data and fault detection of the shared logical memory module.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.