Method of generating finite state data for designing a cascade decomposed logic circuit
US6367054B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 28, 1999 |
| Grant date | Apr 2, 2002 |
| Priority date | — |
| Expiry date | Sep 28, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of designing a cascade decomposed sequential circuit is described in which an input state graph for a sequential circuit is used to generate functions defining transitions between states of the sequential circuit. These functions are used to generate sets of states of the sequential circuit and which contain possible states of the sequential circuit. Levels are then assigned to the generated sets and states are assigned to sequential circuit components in accordance with the assigned levels. These assigned states comprise the current states of the sequential circuit components and using these states and the functions, next states for these sequential circuit components are derived.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.