Field effect transistor having high breakdown withstand capacity
US6369424B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 20, 2000 |
| Grant date | Apr 9, 2002 |
| Priority date | — |
| Expiry date | Jun 20, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S370/901
Abstract
A field effect transistor having a high breakdown withstand capacity is provided. An active region 7a is surrounded by a fixed potential diffusion layer 16, and a channel region 15 is formed in the active region 7a. A gate pad 35 is provided outside the fixed potential diffusion layer 16. Minority carriers injected at a peripheral region of the active region 7a flow into the fixed potential diffusion layer 16, which prevents breakdown attributable to concentration of the carriers. The fixed potential diffusion layer 16 is surrounded by a plurality of guard ring diffusion layers 171 through 174, and a pad diffusion layer 18 formed in a position under the gate pad 35 is connected to the innermost guard ring diffusion layer 171. Since this encourages expansion of a depletion layer under the gate pad 35, an increased breakdown voltage is provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.