Conditioning semiconductor-on-insulator transistors for programmable logic devices
US6369608B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 18, 2001 |
| Grant date | Apr 9, 2002 |
| Priority date | — |
| Expiry date | Jan 18, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17792
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Method and apparatus for preconditioning and in-use conditioning of transistors formed on a semiconductor-on-insulator structure is described. More particularly, transistors of a programmable logic device (PLD), such as a field programmable gate array (FPGA), are preconditioned to take advantage of charge accumulation owing to a “floating body” effect. This preconditioning takes a form of switching transistors on and off prior to customer operation. Accordingly, semiconductor-on-insulator transistors accumulate charge during this switching period, so when customer operation takes place, transistor switching times are less variable over a period of operation of the PLD. Additionally, a design process and implementation is described for identification and in-use conditioning of transistors that may need conditioning during customer operation to control switching time variability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.