Reconfigurable multiplier array
US6369610B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 10, 2000 |
| Grant date | Apr 9, 2002 |
| Priority date | — |
| Expiry date | Oct 10, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17732
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
This invention provides a logic block comprising an mxn array of partial calculating circuits (where m≧2 and n≧2) operable to generate partial product components of an m-bit multiplicand x n-bit multiplicand binary multiplication and to generate a cumulative sum of the partial products for each bit of one of the multiplicands. A configurable output circuit which is operable under the control of a configuration signal either (a) to sum the cumulative sums of partial products generated by the partial calculating circuits so as to generate a product value, or (b) to pass data representing the cumulative sums of the partial product components to partial calculating circuits within one or more further logic blocks. Also provided is a logic circuit including two or more such logic blocks, data interconnections for data transfer between the logic blocks and control interconnections for control signal transfer to the logic blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.