Clock doubler circuit with RC-CR phase shifter network
US6369622B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 1999 |
| Grant date | Apr 9, 2002 |
| Priority date | — |
| Expiry date | Sep 29, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03B19/14
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase shifter network receives at an input node an input clock signal which does not contain higher order harmonics and generates first and second phase-shifted clock signals which are 90° apart and which have the same frequency as the input clock signal. First and second voltage comparators receive the first and second phase-shifted clock signals, respectively, and generates first and second squared clock signals, respectively, which are 90° apart and which have the same frequency as the input clock signal. A combiner combines the first and second squared clock signals to produce an output clock signal having twice the frequency of the input clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.