Programmable phase shift circuitry
US6369624B1 · kind B1 · utility
46Cited by
12References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 2, 1999 |
| Grant date | Apr 9, 2002 |
| Priority date | — |
| Expiry date | Nov 2, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00045
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field programmable gate array (FPGA) to provide additional programmability features. The programmable phase shift circuitry may be implemented within a phase locked loop (PLL) or delay locked loop (DLL) circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.