Simultaneous nulling in low sidelobe sum and difference antenna beam patterns
US6369746B1 · kind B1 · utility
2Cited by
13References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 13, 2000 |
| Grant date | Apr 9, 2002 |
| Priority date | — |
| Expiry date | Jul 13, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01Q25/02
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A radar system includes a null processor coupled to transmit receive modules. The null processor inserts nulls in the sum pattern at locations for suppressing a jamming source. The null processor determines the difference pattern based upon the product: sum*sin(x), where sum is the sum pattern and x is the azimuth angle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.