Synchronous signal detection circuit and method
US6369856B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 30, 1998 |
| Grant date | Apr 9, 2002 |
| Priority date | — |
| Expiry date | Jun 30, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N5/10
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A synchronous signal detection circuit which detect a vertical synchronous signal and a horizontal synchronous signal from composite synchronous signal, including: a reset generation means for receiving an external composite synchronous signal and an external main clock signal to generate a reset signal at falling edge of the composite synchronous signal; a counter means being reset by the reset signal received from the reset generation means and for counting the main clock signal to generate first through fourth output signals; a vertical synchronous signal detection means for receiving the second output signal of the counter means and the composite synchronous signal to detect the vertical synchronous signal of the composite synchronous signal and generating the vertical synchronous signal; and a horizontal synchronous signal detection means for receiving the third and the fourth output signals of the counter means and the reset signal of the reset generation means to detect the horizontal synchronous signal of composite synchronous signal having a period of 1 horizontal scanning interval (1H).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.